View MAX2079_9059601.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 general description the MAX2079 fully integrated octal ultrasound receiver is optimized for high channel count, high-performance portable and cart-based ultrasound systems. the easy- to-use integrated receiver allows the user to achieve high-end 2d and doppler imaging capability using substantially less space and power. the highly compact low-noise amplifier (lna), variable-gain amplifier (vga), anti-alias filter (aaf), analog-to-digital converter (adc), and digital highpass filter (hpf) achieve an ultra-low 2.8db noise figure at r s = r in = 200 i with a very low 120mw per channel power dissipation at 50msps. the full receive channel has been optimized for second- harmonic imaging with an exceptional 76dbfs snr over a 2mhz bandwidth, and -70dbc second-harmonic distortion at f rf = 5mhz over the full receiver gain range. near-carrier dynamic range has also been optimized for exceptional pulsed and color-flow doppler performance under high-clutter conditions. the bipolar front-end and cmos adc achieve an exceptional near-carrier snr of 137dbfs/hz at 1khz from a 5mhz tone for excellent low- velocity doppler sensitivity. the device also includes an octal cwd beamformer for a full doppler solution. separate mixers for each channel are available for optimal cwd sensitivity. the MAX2079 octal ultrasound front-end is available in a small, 10mm x 10mm, ctbga package and is specified over the 0 n c to +70 n c temperature range. applications medical ultrasound imagingsonar benefits and features s minimizes pcb area and design cost ? 8 full channels of lna, vga, aaf, 12-bit adc, digital hpf and cwd mixer beamformer in a small, 10mm x 10mm ctbga package s improves system sensitivity ? ultra-low full-channel noise figure of 2.8db at r s = r in = 200 i s improves system dynamic range ? 76dbfs image path snr over 2mhz bandwidth at f rf = 5mhz ? 137dbfs/hz image path snr at 1khz offset from f rf = 5mhz s consumes less power ? ultra-low power of only 120mw per full channel in imaging mode at 50msps s selectable active input impedance matching of 50 i , 100 i , 200 i , and 1k i s programmable vga output clamp s integrated selectable 3-pole 9mhz, 10mhz, 15mhz, and 18mhz butterworth anti-alias filter s programmable, digital highpass, 2-pole filter s serial lvds digital outputs s fast recovery low-power modes (< 2s) s separate channel i/q cwd mixers for improved dynamic range and sensitivity 19-5901; rev 1; 10/12 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX2079.related . for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim?s website at www.maximintegrated.com. downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 2 maxim integrated v cc3, v cc5 to gnd .............................................. -0.3v to +5.5v avdd, ovdd to gnd .......................................... -0.3v to +2.1v v cc5 - v cc3 ................................................................... > -0.3v v ref , lo+/-, gc+/- to gnd .................... -0.3v to (v cc3 + 0.3v) ci+/-, cq+/- to gnd ............................................. -0.3v to +13v zf_, in_, ag to gnd ............................... -0.3v to (v cc5 + 0.3v) inc_ ........................................................................... 20ma dc in_ to ag .............................................................. -0.6v to +0.6v refio, clkin+/-, loon to gnd ........... -0.3v to the lower of (v avdd + 0.3v) and +2.1v out+/-, sdio, sclk, cs , clkout+/-, frame+/-, shdn, cwd to gnd .... -0.3v to the lower of (v ovdd + 0.3v) and +2.1v ci+/-, cq+/-, v cc5 , v cc3, avdd/ovdd, v ref analog and digital control signals must be applied in this order. input differential voltage ............................... 2.0v p-p differential continuous power dissipation (t a = +70 n c) 144-bump ctbga (derate 33.3mw/ n c above +70 n c) .... 3200mw operating case temperature range (note 1) .... 0 n c to +70 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -40 n c to +150 n c soldering temperature (reflow) ...................................... +260 n c junction-to-ambient thermal resistance ( q ja ) .............. 25c/w junction-to-case thermal resistance ( q jc ) .................. 7.7c/w absolute maximum ratings note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . note 1: t c is the temperature on the bump of the package. t a is the ambient temperature of the device and pcb. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 2) octal ultrasound front-end specifications dc electrical characteristics?vga mode (cwd beamformer off) (v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, t a = 0 n c to +70 n c, v gnd = 0v, shdn = 0, cwd = 0, loon = 0, f rf = 5mhz, 50mv p-p , adc f clk = 50msps, digital hpf set to 60/64, two poles, 15/16 digital gain, v gc+ - v gc- = -3v (minimum gain), high lna gain. typical values are at v ref = 2.5v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc- = 0v, t a = +25 n c, unless otherwise noted.) (note 3) parameter symbol conditions min typ max units 3.3v supply voltage v cc3 v cc3 pins 3.13 3.3 3.47 v 5v supply voltage v cc5 v cc5 pins 4.5 4.75 5.25 v 1.8v supply voltage v cc1.8 avdd and ovdd pins 1.7 1.8 1.9 v external reference voltage range v ref (note 4) 2.475 2.525 v external reference current total current into the v ref pin 5 f a 3v supply current per channel i cc3 total i divided by 8, v gc+ - v gc- = 0.4v 9.5 16 ma 5v supply current per channel i cc5 total i divided by 8 6.4 9 ma 1.8v supply currentper channel i cc1.8 total i divided by 8, avdd + ovdd 32 37.9 ma total i divided by 8, avdd 20 22.8 ma total i divided by 8, ovdd 12 15.1 ma dc power per channel p_nm v gc+ - v gc- = -0.4v 120 mw differential analog control voltage range vgain_rang v gc+ - v gc- q 3 v downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 3 maxim integrated ac electrical characteristics?vga mode (cwd beamformer off)(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, t a = 0 n c to +70 n c, v gnd = 0v, shdn = 0, cwd = 0, loon = 0, f rf = 5mhz, 50mv p-p , adc f clk = 50msps, digital hpf set to 60/64, two poles, 15/16 digital gain, v gc+ - v gc- = -3v (minimum gain), high lna gain. typical values are at v ref = 2.5v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc - = 0v, t a = +25 n c, unless otherwise noted.) (note 3) dc electrical characteristics?vga mode (cwd beamformer off) (continued) (v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, t a = 0 n c to +70 n c, v gnd = 0v, shdn = 0, cwd = 0, loon = 0, f rf = 5mhz, 50mv p-p , adc f clk = 50msps, digital hpf set to 60/64, two poles, 15/16 digital gain, v gc+ - v gc- = -3v (minimum gain), high lna gain. typical values are at v ref = 2.5v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc- = 0v, t a = +25 n c, unless otherwise noted.) (note 3) parameter symbol conditions min typ max units 5v supply nap current i_np_5v_tot shdn = 1, nap mode (all 8 channels) 30 ma 3v supply nap current i_np_3v_tot shdn = 1, nap mode (all 8 channels) 0.035 ma 1.8v supply nap current shdn = 1, nap mode (all 8 channels) 40 ma 5v supply power-down current i_pd_5v_tot shdn = 1, power-down mode(all 8 channels) 1 f a 3v supply power-down current i_pd_3v_tot shdn = 1, power-down mode(all 8 channels) 1 f a 1.8v supply power-down current shdn = 1, power-down mode(all 8 channels) 0.38 ma common-mode voltage for differential analog control vgain_comm (v gc+ - v gc- )/2 1.65 5% v source/sink current for gain control pins i_acontrol per pin 1.6 a parameter conditions min typ max units adc bits 12 bits minimum adc sample rate 25 msps maximum adc sample rate 50 msps mode-select response time (note 5) cwd stepped from 0 to 1, dc stable within 10% 1 f s cwd stepped from 1 to 0, dc stable within 10% 1 input impedance 50 i mode, f rf = 2mhz 50 i 100 i mode, f rf = 2mhz 100 200 i mode, f rf = 2mhz 200 1k i mode, f rf = 2mhz 1000 noise figure (high lna gain) r s = r in = 50 i , v gc+ - v gc- = +3v 4.8 db r s = r in = 100 i , v gc+ - v gc- = +3v 3.8 r s = r in = 200 i , v gc+ - v gc- = +3v 2.8 r s = r in = 1000 i , v gc+ - v gc- = +3v 2.5 noise figure (low lna gain) r s = r in = 200 i , v gc+ - v gc- = +3v 3.8 db downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 4 maxim integrated ac electrical characteristics?vga mode (cwd beamformer off) (continued) (v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, t a = 0 n c to +70 n c, v gnd = 0v, shdn = 0, cwd = 0, loon = 0, f rf = 5mhz, 50mv p-p , adc f clk = 50msps, digital hpf set to 60/64, two poles, 15/16 digital gain, v gc+ - v gc- = -3v (minimum gain), high lna gain. typical values are at v ref = 2.5v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc - = 0v, t a = +25 n c, unless otherwise noted.) (note 3) parameter conditions min typ max units 8-channel correlated noise power no input signal, ratio of 8-channel noise power to single-channel noise power 9.0 db 5mhz signal applied to all 8 channels, v gc+ - v gc- = 0v , f rf = 5mhz at -3dbfs, ratio of 8-channel noise power to single-channel noise power 8.5 lna gain (low lna gain) 12.5 db lna gain (high lna gain) 18.5 db maximum gain (high lna gain) v gc+ - v gc- = +3v (max gain), lna input to adc input 44.7 db minimum gain (high lna gain) v gc+ - v gc- = -3v (min gain), lna input to adc input 5.9 db maximum gain (low lna gain) v gc+ - v gc- = +3v (max gain), lna input to adc input 40.4 db minimum gain (low lna gain) v gc+ - v gc- = = -3v (min gain), lna input to adc input 1.4 db gain range 38.8 db aa filter 3db corner frequency 9mhz setting 9 mhz 10mhz setting 10 15mhz setting 15 18mhz setting 18 aa filter 3db corner frequency accuracy q 10 % digital highpass filter 3db corner frequency 2 poles, coefficients r1 = r2 = 63/64, f clk = 50msps 0.185 mhz 2 poles, coefficients r1 = r2 = 54/64, f clk = 50msps 1.736 clamp level clamp on (v p-p on aaf output/adc input, digital hpf bypassed) 92 %fs device-to-device gain matching t a = +25 n c, v gc+ - v gc- = -3v to +3v (note 6) -1.6 q 0.5 +1.6 db input gain compression lna = high gain, v gc+ - v gc- = -3v (vga = min gain), gain ratio with 330mv p-p /50mv p-p input tones 0.7 db lna = low gain, v gc+ - v gc- = -3v (vga = min gain), gain ratio with 600mv p-p /50mv p-p input tones 0.9 vga gain response time gain step up (v in = 5mv p-p , v gc+ - v gc- changed from -3v to +3v, settling time is measured within 1db final value) 0.8 f s gain step down (v in = 5mv p-p , v gc+ - v gc- changed from -3v to +3v, settling time is measured within 1db final value) 1.8 vga output offset under pulsed overload over drive is q 10ma in clamping diodes, v gc+ - v gc- = 1.0v (gain = 30db), 16 pulses at 5mhz, repetition rate 20khz; offset is measured at output when rf duty cycle is off < 3.3 %fs signal-to-noise over adc nyquist band (25mhz) v out_ = -1dbfs, v in = 200mv p-p , f rf = 5mhz at -1dbfs, anti-alias filter = 9mhz, 50msps sample rate 67 dbfs downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 5 maxim integrated ac electrical characteristics?vga mode (cwd beamformer off) (continued) (v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, t a = 0 n c to +70 n c, v gnd = 0v, shdn = 0, cwd = 0, loon = 0, f rf = 5mhz, 50mv p-p , adc f clk = 50msps, digital hpf set to 60/64, two poles, 15/16 digital gain, v gc+ - v gc- = -3v (minimum gain), high lna gain. typical values are at v ref = 2.5v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc - = 0v, t a = +25 n c, unless otherwise noted.) (note 3) dc electrical characteristics?cwd mode (vga, aaf, and adc off)(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, t a = 0 n c to +70 n c, v gnd = 0v, shdn = 0, cwd = 1, loon = 1, r in = 200 i , high lna gain, ci+, ci-, cq+, cq- pulled up to +11v through four separate 0.1% 120 i resistors. no rf signals applied. typical values are at v ref = 2.5v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, t a = +25 n c, unless otherwise noted.) (note 3) parameter conditions min typ max units signal-to-noise over 2mhz bandwidth v out_ = -1dbfs, v in = 200mv p-p , f rf = 5mhz at -1dbfs, anti-alias filter = 9mhz, 50msps sample rate 76 dbfs near-carrier signal-to-noise ratio v gc+ - v gc- = 0v (gain = 22db), f rf = 5.3mhz at -0.5dbfs, measured at 1khz from f rf , 50msps sample rate -137 dbfs/hz second harmonic (hd2) v in = 50mv p-p , f rf = 2mhz, adc out = -3dbfs -71 dbc v in = 50mv p-p , f rf = 5mhz, adc out = -3dbfs -70 im3 distortion v in = 50mv p-p , f rf1 = 5mhz, f rf2 = 5.01mhz adc out = -3dbfs (note 7) -54 dbc nap mode power-up response time v gc+ -v gc- = 0.6v (gain = 28db), f rf = 5mhz, adc out = -3dbfs, settled with in 1db from transition on shdn pin (includes adc) 2 f s nap mode power-down response time to reach dc current target q 10%, on v cc5 , v cc3 , avdd, ovdd from transition on shdn pin 4 f s sleep mode power-up response time v gc+ - v gc- = 0.6v (gain = 28db), f rf = 5mhz, v out_ = -1dbfs, settled within 1db from transition on shdn 2 ms sleep mode power-down response time v gc+ - v gc- = 0.6v (gain = 28db), f rf = 5mhz, dc power reaches 1mw/channel, from transition on shdn (includes adc) 4 ms adjacent-channel crosstalk v out_ = -3dbfs, f rf = 5mhz, v gc+ - v gc- = 0.6v (gain = 28db) -60 dbc alternate-channel crosstalk v out_ = -3dbfs, f rf = 5mhz, v gc+ - v gc- = 0.6v (gain = 28db) -80 dbc phase matching between channels v gc+ -v gc- = 0.6v (gain = 28db), f rf = 5mhz, v out_ = -3dbfs q 1.2 degrees parameter symbol conditions min typ max units mixer lvds lo input common-mode voltage v_lvds_cm pins lo+ and lo- 1.25 q 0.2 v lvds lo differential input voltage v_lvds_dm common-mode input voltage = 1.25v(note 8) 200 700 mv p-p lvds lo input common-mode current i_lvds_cm input bias current, common-mode input voltage = 1.25v (note 8) 160 f a downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 6 maxim integrated dc electrical characteristics?cwd mode (vga, aaf, and adc off ) (continued) (v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, t a = 0 n c to +70 n c, v gnd = 0v, shdn = 0, cwd = 1, loon = 1, r in = 200 i , high lna gain, ci+, ci-, cq+, cq- pulled up to +11v through four separate 0.1% 120 i resistors. no rf signals applied. typical values are at v ref = 2.5v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, t a = +25 n c, unless otherwise noted.) (note 3) parameter symbol conditions min typ max units lvds lo differential input resistance r_lvds_dm (note 9) 8 k i full-power mode5v supply current per channel i_c_5v_f total i divided by 8 31.6 41 ma 3.3v supply current per channel i_c_3_3v_f total i divided by 8 1.8 3 ma 1.8v supply current per channel i_c_1_8v_f total i divided by 8, avdd + ovdd 6.3 ma 11v supply current per channel i_c_11v_f total i divided by 8 11.7 16.2 ma external reference current total current into v ref pin 70 f a on-chip power dissipation(all 8 channels) pdis_fp_tot_f (note 11) 2.1 w on-chip power dissipation per channel pdis_fp_f (note 11) 260 mw 5v power-down current shdn = 1, power-down mode (all 8 channels) 1 f a 3v power-down current shdn = 1, power-down mode (all 8 channels) 1 f a 1.8v supply power-down current shdn = 1, power-down mode (all 8 channels) 0.38 ma low-power mode5v supply current per channel i_c_5v_l total i divided by 8 27 35 ma 3.3v supply current per channel i_c_3_3v_l total i divided by 8 1.8 3 ma 1.8v supply current per channel i_c_1_8v_l total i divided by 8, avdd + ovdd 6.3 ma 11v supply current per channel i_c_11v_l total i divided by 8 7 ma on-chip power dissipation(all 8 channels) pdis_fp_tot_l (note 11) 1.6 w on-chip power dissipation per channel pdis_fp_l (note 11) 200 mw downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 7 maxim integrated ac electrical characteristics?cwd mode (vga, aaf, and adc off)(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, t a = 0 n c to +70 n c, v gnd = 0v, shdn = 0, cwd = 1, shdn = 0, loon = 1, r in = 200 i , f rf = 5mhz, source resistance r s = 200 i , ci+, ci-, cq+, cq- pulled up to +11v through four separate 0.1% 120 i resistors). the rise/fall time of the lvds clock driving lo+/lo- is required to be 0.5ns, refer - ence noise less than 10nv/ hz from 1khz to 20mhz (note 10). typical values are at v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, t a = +25 n c, unless otherwise noted.) (note 3) parameter conditions min typ max units cw dopper mixermixer rf frequency range 0.9 7.6 mhz lo frequency range 8.0 60 mhz mixer output frequency range dc 100 khz full-power mode noise figure no carrier 4.8 db snr at 100mv p-p input 100mv p-p on input, f rf = f lo /8 = 1.25mhz, measured at 1khz offset 146 dbc/hz snr at 200mv p-p input 200mv p-p on input, f rf = f lo /8 = 1.25mhz, measured at 1khz offset 151 dbc/hz im3 distortion v in = 100mv p-p , f rf1 = 5mhz, f rf2 = 5.01mhz, f lo = 8 x 5mhz (note 7) -57 dbc mixer output-voltage compliance valid voltage range (ac + dc) on summed mixer output pins (note12) 4.5 12 v channel-to-channel phase matching measured under zero beat conditions. v in = 100mv p-p , f rf = 5mhz, f lo /8 = 5mhz -1 q 0.5 +1 degrees channel-to-channel gain matching measured under zero beat conditions v in = 100mv p-p , f rf = 5mhz, f lo /8 = 5mhz -1 q 0.5 +1 db transconductance f lo /8 = 1.25mhz (note 13) 19 23 26.5 ms low-power mode noise figure no carrier 4.8 db snr at 100mv p-p input 100mv p-p on input, f rf = f lo /8 = 1.25mhz, measured at 1khz offset 146 dbc/hz snr at 200mv p-p input 200mv p-p on input, f rf = f lo /8 = 1.25mhz, measured at 1khz offset 150 dbc/hz im3 distortion v in = 100mv p-p , f rf1 = 5mhz, f rf2 = 5.01mhz, f lo = 8 x 5mhz (note 7) -44 dbc mixer output-voltage compliance valid voltage range (ac + dc) on summed mixer output pins (note 12) 4.5 12 v transconductance f lo /8 = 1.25mhz (note 13) 18 22 25.5 ms downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 8 maxim integrated electrical characteristics?clock and timing(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, t a = 0 n c to +70 n c, v gnd = 0v, shdn = 0, cwd = 0, loon = 0. f rf = 5mhz, 50mv p-p , adc f clk = 50msps, digital hpf set to 60/64, two poles, 15/16 digital gain, v gc+ - v gc- = -3v (minimum gain), high lna gain. typical values are at v ref = 2.5v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc- = 0v, t a = +25 n c, unless otherwise noted.) (note 3) parameter symbol conditions min typ max units clock inputs (clkin+, clkin-), differential modedifferential clock input voltage 0.4 to 2.0 v p-p common-mode voltage v clkcm self-biased 1.2 v dc-coupled clock signal 1.0 to 1.4 input resistance r clk differential, default setting 10 k i differential, programmable internal termination selected 0.1 common mode to gnd 9 input capacitance c clk capacitance to gnd, each input 3 pf clock inputs (clkin+, clkin-), single-ended mode (clkin- < 0.1v)single-ended mode-selection threshold (clkin-) 0.1 v single-ended clock input high threshold (clkin+) 1.5 v single-ended clock input low threshold (clkin+) 0.3 v input leakage (clkin+) v ih = 1.8v +5 f a v il = 0v -5 input leakage (clkin-) v il = 0v -150 -50 f a input capacitance (clkin+) 3 pf digital inputs (cwd, loon, shdn, sclk, sdio, cs ) input high threshold v ih 1.5 v input low threshold v il 0.3 v input leakage i ih v ih = 1.8v +5 f a i il v il = 0v -5 input capacitance c din 3 pf digital outputs (sdio)output voltage low v ol i sink = 200 f a 0.2 v output voltage high v oh i source = 200 f a ovdd - 0.2 v lvds digital outputs (out_+/-, clkout+/-, frame+/-) (i = 3.5ma, vcm = 1.2v) differential output voltage | v od | r load = 100 i 225 300 490 mv output offset voltage v os 1.125 1.200 1.375 v downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 9 maxim integrated electrical characteristics?clock and timing (continued)(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, t a = 0 n c to +70 n c, v gnd = 0v, shdn = 0, cwd = 0, loon = 0. f rf = 5mhz, 50mv p-p , adc f clk = 50msps, digital hpf set to 60/64, two poles, 15/16 digital gain, v gc+ - v gc- = -3v (minimum gain), high lna gain. typical values are at v ref = 2.5v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc- = 0v, t a = +25 n c, unless otherwise noted.) (note 3) parameter symbol conditions min typ max units serial-port interface timingsclk period t sclk 50 ns sclk-to- cs setup time t css 10 ns sclk-to- cs hold time t csh 10 ns sdio-to-sclk setup time t sds serial-data write 10 ns sdio-to-sclk hold time t sdh serial-data write 0 ns sclk-to-sdio output data delay t sdd serial-data read 10 ns lvds digital output timing characteristicsdata valid to clkout_ rise/fall t od (t sample / 24) - 0.10 (t sample / 24) + 0.05 (t sample / 24) + 0.20 ns clkout_ output-width high t ch t sample / 12 ns clkout_ output-width low t cl t sample / 12 ns frame_ rise to clkout_ rise t df (t sample / 24) - 0.10 (t sample / 24) + 0.05 (t sample / 24) + 0.20 ns sample clkin_ rise toframe_ rise t sf (t sample / 2) + 1.6 (t sample / 24) + 2.3 (t sample / 2) + 3.3 ns cwd lo timingloon setup time t su setup time from loon high to lvds lo clock low-to-high transition 5 ns downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 10 maxim integrated electrical characteristics?clock and timing (continued)(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, t a = 0 n c to +70 n c, v gnd = 0v, shdn = 0, cwd = 0, loon = 0. f rf = 5mhz, 50mv p-p , adc f clk = 50msps, digital hpf set to 60/64, two poles, 15/16 digital gain, v gc+ - v gc- = -3v (minimum gain), high lna gain. typical values are at v ref = 2.5v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc- = 0v, t a = +25 n c, unless otherwise noted.) (note 3) note 3: minimum and maximum limits at t a = +25 n c and +70 n c are guaranteed by production test. specifications for t a < +25 n c are guaranteed by design and/or characterization. note 4: noise performance of the device is dependent on the noise contribution from v ref . use a low-noise supply for v ref . note 5: this response time does not include the cw output highpass filter. when switching to vga mode, the cw outputs stop drawing current and the output voltage goes to the rail. if a highpass filter is used, the recovery time can be excessive and a switching network is recommended. note 6: specifications are guaranteed by design and characterization. note 7: see figure 22 in the ultrasound-specific imd3 specification section. note 8: the lvds cwd lo inputs are dc-coupled. see the cwd beamformer programming and clocking section for details of lo startup synchronization. note 9: an external 100 i resistor terminates the lvds differential signal path (lo+, lo-). note 10: the reference input noise is given for 8 channels, knowing that the reference-noise contributions are correlated in all 8 channels. if more channels are used, the reference noise must be reduced to get the best noise performance. note 11: total on-chip power dissipation is calculated as p diss = v cc5 x i cc5 + v cc3 x i cc3 + v avdd x i avdd + v ovdd x i ovdd + v ref x i ref + [11v - (i 11v /4) x 120] x i 11v . additional power is dissipated through the off-chip 120 i load resistors. note 12: mixer output-voltage compliance is the range of acceptable voltages allowed on the cw mixer outputs. note 13: transconductance is defined as the differential output current at baseband for each individual (i or q) mixer output, divided by the single-ended rf input voltage directly on a single lna input pin (inj). this can be calculated as g mi = (i ci+ - i ci- )/v inj and g mq = (i cq+ - i cq- )/v inj ; or equivalently as g mi = (v ci+ - v ci- )/(r l x v inj ) and g mq = (i cq+ - i cq- )/ (r l x v inj ) (where j = 1, 2, ?8 is a specific channel number, inj is a single lna input pin, and r l is the load resistance on each individual mixer output pin). cwd loon (lo on/off) timing detail t su lo+ lvds lo lo- loon downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 11 maxim integrated typical operating characteristics (typical values are at v ref = 2.5v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc- = 0v, t a = +25c, unless otherwise noted.) (note 3) gain vs. differential analog control voltage MAX2079 toc01 control voltage (v) gain (db) 2 1 0 -1 -2 10 20 30 40 50 0 -3 3 complex input impedance magnitude vs. frequency (lna gain = 18.5db, 200 i ) MAX2079 toc04 input impedance, real part ( i ) 20 15 10 5 50 100 150 200 250 0 02 5 -120-140 -100 -80 -60 -40 -20 0 input impedance, imaginary part ( i ) frequency (mhz) real imaginary complex input impedance magnitude vs. frequency (lna gain = 18.5db, 50 i ) MAX2079 toc02 frequency (mhz) input impedance, real part ( i ) 20 15 10 5 10 20 30 40 50 60 70 80 90 0 -10 0 10 20 30 40 50-20 02 5 input impedance, imaginary part ( i ) imaginary real frequency (mhz) input impedance, real part ( i ) 20 15 10 5 200 400 600 800 1000 1200 0 02 5 complex input impedance magnitude vs. frequency (lna gain = 18.5db, 1000 i ) MAX2079 toc05 -300-400 -500 -200 -100 0-600 input impedance, imaginary part ( i ) real imaginary complex input impedance magnitude vs. frequency (lna gain = 18.5db, 100 i ) MAX2079 toc03 frequency (mhz) input impedance, real part ( i ) 20 15 10 5 20 40 60 80 100 120 140 160 180 0 -15-20 -25 -10 -5 0 5 10 15-30 02 5 input impedance, imaginary part ( i ) real imaginary gain distribution (v gc+ - v gc- = 0v) MAX2079 toc06 5 10 15 20 25 30 35 0 21.821.9 22.0 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 22.9 23.0 % occurrence gain (db) downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 12 maxim integrated typical operating characteristics (continued) (typical values are at v ref = 2.5v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc- = 0v, t a = +25c, unless otherwise noted.) (note 3) second-harmonic distortion vs. gain (aaf = 9mhz) MAX2079 toc10 gain (db) hd2 (dbc) 38 32 26 -80 -70 -60 -50 -40 -30 -90 20 44 f rf = 10mhz f rf = 2mhz f rf = 5mhz v out = -3.5dbfs (1v p-p ) v in 100mv p-p second-harmonic distortion vs. gain (aaf = 18mhz) MAX2079 toc13 gain (db) hd2 (dbc) 38 32 26 -80 -70 -60 -50 -40 -30-90 20 44 f rf = 5mhz f rf = 2mhz f rf = 10mhz v out = -3.5dbfs (1v p-p ) v in 100mv p-p second-harmonic distortion vs. gain (aaf = 10mhz) MAX2079 toc11 gain (db) hd2 (dbc) 38 32 26 -80 -70 -60 -50 -40 -30 -90 20 44 f rf = 10mhz f rf = 2mhz v out = -3.5dbfs (1v p-p ) v in 100mv p-p f rf = 5mhz third-harmonic distortion vs. gain (aaf = 9mhz) MAX2079 toc14 gain (db) hd3 (dbc) 38 32 26 -90 -80 -70 -60 -50 -40 -100 20 44 f rf = 5mhz v out = -3.5dbfs (1v p-p ) v in 100mv p-p f rf = 10mhz f rf = 2mhz second-harmonic distortion vs. gain (aaf = 15mhz) MAX2079 toc12 gain (db) hd2 (dbc) 38 32 26 -80 -70 -60 -50 -40 -30-90 20 44 f rf = 10mhz f rf = 2mhz v out = -3.5dbfs (1v p-p ) v in 100mv p-p f rf = 5mhz third-harmonic distortion vs. gain (aaf = 10mhz) MAX2079 toc15 gain (db) hd3 (dbc) 38 32 26 -90 -80 -70 -60 -50 -40 -100 20 44 f rf = 2mhz v out = -3.5dbfs (1v p-p ) v in 100mv p-p f rf = 5mhz f rf = 10mhz total output noise (afe + adc) vs. gain MAX2079 toc07 gain (db) output noise at 5mhz (nv/ hz) 40 30 20 10 50 100 150 200 250 0 05 0 aaf = 9mhz total output noise vs. gain MAX2079 toc08 gain (db) total output noise (dbfs) 40 30 20 10 -65 -60 aaf = 15mhz aaf = 9mhz aaf = 10mhz -55 -50-70 05 0 aaf = 18mhz total input noise (afe + adc) vs. gain MAX2079 toc09 gain (db) total input noise at 5mhz (nv/ hz) 35 25 15 5 10 15 20 25 30 0 54 5 aaf = 9mhz downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 13 maxim integrated typical operating characteristics (continued) (typical values are at v ref = 2.5v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc- = 0v, t a = +25c, unless otherwise noted.) (note 3) im3 vs. gain MAX2079 toc19 gain (db) im3 (dbc from small signal) 40 30 20 -70 -65 -60 -55 -50 -45 -40-75 10 50 f 1 = 5mhz, v in at f 1 = 50mv p-p (gain p 27db) v out at f 1 = -3dbfs (gain > 27db) f 2 = 5.01mhz, v in at f 2 = -25dbc adjacent channel-to-channel crosstalk vs. gain (5mhz) MAX2079 toc22 gain (db) crosstalk (dbc) 41 35 29 23 17 11 -65 -60 -55 -50 -45 -40-70 54 7 adjacent channel 1 adjacent channel 2 v out = -3.5dbfs (1v p-p ) when gain 16db h2, h3 vs. adc output MAX2079 toc20 signal out (dbfs) harmonic (dbc) -5 -10 -15 -85 -80 -75 -70 -65 -60 -55 -50-90 -20 0 h2 h3 v in = 10mv p-p at 5mhz alternate channel-to-channel crosstalk vs. gain (5mhz) MAX2079 toc23 gain (db) crosstalk (dbc) 41 35 29 23 17 11 -65 -60 -55 -50 -45 -40-70 54 7 alternate channel 1 alternate channel 2 v out = -3.5dbfs (1v p-p ) when gain 16db im3 distortion vs. frequency MAX2079 toc21 frequency (mhz) im3 (dbc) 8 6 4 2 -60 -55 -50 -45 -40-65 01 0 v in = 50mv p-p (gain = 21db) adjacent channel-to-channel crosstalk vs. gain (10mhz) MAX2079 toc24 gain (db) crosstalk (dbc) 41 35 11 17 23 29 -65 -60 -55 -50 -45 -40 -35 -30-70 54 7 adjacent channel 1 adjacent channel 2 v out = -3.5dbfs (1v p-p ) when gain 16db third-harmonic distortion vs. gain (aaf = 15mhz) MAX2079 toc16 gain (db) hd3 (dbc) 38 32 26 -90 -80 -70 -60 -50 -40 -100 20 44 v out = -3.5dbfs (1v p-p ) v in 100mv p-p f rf = 2mhz f rf = 10mhz f rf = 5mhz third-harmonic distortion vs. gain (aaf = 18mhz) MAX2079 toc17 gain (db) hd3 (dbc) 38 32 26 -90 -80 -70 -60 -50 -40 -100 20 44 v out = -3.5dbfs (1v p-p ) v in 100mv p-p f rf = 2mhz f rf = 10mhz f rf = 5mhz second- and third-harmonic distortion vs. frequency (aaf = 18mhz, gain = 26db) MAX2079 toc18 frequency (mhz) hd2 and hd3 (dbc) 10 5 -85 -80 -75 -70 -65 -60 -55-90 0 v out = -3.5dbfs (1v p-p ) gain = 26db hd2 hd3 downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 14 maxim integrated typical operating characteristics (continued) (typical values are at v ref = 2.5v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc- = 0v, t a = +25c, unless otherwise noted.) (note 3) lna overload recovery (digital hpf disabled) MAX2079 toc30 time (s) code values 8 6 4 2 1024 2048 3072 0 01 0 frequency (mhz) gain (db) 20 15 10 5 0 5 10 15 20 25 -5 02 5 large-signal bandwidth vs. frequency (gain = 20db) MAX2079 toc28 10mhz 18mhz 9mhz 15mhz v out = -3.5dbfs (1v p-p ) gain = 20 d b large-signal bandwidth vs. frequency (gain = 20db) MAX2079 toc29 frequency (mhz) gain (db) 1 0 5 10 15 20 25 -5 0.1 10 v out = -3.5dbfs (1v p-p ) gain = 20db 18mhz 9mhz 10mhz 15mhz vga overload recovery MAX2079 toc32 time (s) code values 10 12 14 68 4 2 15361024 512 2048 30722560 3584 46084096 5120 61445632 0 input (mv) -100-120 -80 -40-60 -20 200 01 6 input output gain = max lna overload recovery (digital hpf enabled) MAX2079 toc31 time (s) code values 5 4 3 2 1 1024 2048 3072 4096 0 06 tx pulse 5mhz, 6v p-p from open-circuit source, 16 cycles, 50s period gain = 30db rf input = 5mhz, 6.4mv p-p cw -80 -60 -40 -20 0 -100 11 0 MAX2079 toc27 frequency (mhz) crosstalk (dbc) v out = -3.5dbfs (1v p-p ) v in = 100mv p-p frequency < 10mhz aaf = 18mhz alternate channel 1 alternate channel 2 alternate channel-to-channel crosstalk vs. frequency alternate channel-to-channel crosstalk vs. gain (10mhz) MAX2079 toc25 gain (db) crosstalk (dbc) 41 35 29 23 17 11 -85 -80 -75 -70 -65 -60-90 54 7 alternate channel 1 alternate channel 2 v out = -3.5dbfs (1v p-p ) when gain 16db adjacent channel-to-channel crosstalk vs. frequency MAX2079 toc26 frequency (mhz) crosstalk (dbc) -60 -40 -20 0 -80 11 0 v out = -3.5dbfs (1v p-p ) v in = 100mv p-p frequency < 10mhz aaf = 18mhz adjacent channel 1 adjacent channel 2 downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 15 maxim integrated typical operating characteristics (continued) (typical values are at v ref = 2.5v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc- = 0v, t a = +25c, unless otherwise noted.) (note 3) snr vs. adc output level MAX2079 toc36 output (dbfs) snr (dbfs) -2 -4 -6 -8 66.9 67.0 67.1 67.2 67.3 67.4 67.5 67.6 67.766.8 -10 0 v in = 200mv p-p at 5mhz vga gain control response time (up) MAX2079 toc37 time (s) code values 7 6 5 4 3 2 1 0 -1 1024 2048 3072 4096 0 -2 8 gc q transitionat t = 0 gain max to gain min cwd im3 vs. frequency MAX2079 toc33 rf frequency (mh z ) im3 (dbc) 6 4 2 -58 -56 -54 -52 -50-60 08 v in = 100mv f 2 = -25dbc at an offset of 1khz fft plot (8192 points) MAX2079 toc34 frequency (mhz) amplitude (dbfs) 18 12 6 -100 -80 -60 -40 -20 0 -120 02 4 snr vs. gain MAX2079 toc35 gain (db) snr (dbfs) 35 25 15 55 60 65 7050 54 5 v out = -1dbfs, f in = 5mhz, aaf = 9mhz downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 16 maxim integrated typical operating characteristics (continued) (typical values are at v ref = 2.5v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc- = 0v, t a = +25c, unless otherwise noted.) (note 3) digital highpass filter normalized magnitude responses vs. frequency?first section (hpf1) MAX2079 toc39 frequency (mhz) normalized gain (db) -20 -15 -10 -5 0 5 10 -25 0.1 1 r1 = bypass r1 = 54/64 r1 = 63/64 digital highpass filter normalized magnitude responses vs. frequency?second section (hpf2) MAX2079 toc40 frequency (mhz) normalized gain (db) -20 -15 -10 -5 0 5 10 -25 0.1 1 r2 = bypass r2 = 54/64 r2 = 63/64 vga gain control response time (down) MAX2079 toc38 time (s) code values 7 6 5 4 3 2 1 0 -1 1024 2048 3072 4096 0 -2 8 gc +/- transition at t = 0 gain max to gain min digital highpass filter normalized magnitude responses vs. frequency? two cascaded sections (hpf1 + hpf2) MAX2079 toc41 frequency (mhz) normalized gain (db) -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 -50 0.1 1 r1 = r2 = 63/64 r1 = r2 = 54/64 r1 = r2 = bypass downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 17 maxim integrated bump configuration gnd gndgnd ag gnd ag clkout- frame- out4- gnd gnd gnd gnd lo- gnd out3+ out4+ gnd gnd gnd out3- gnd inc6 in6 loon avdd gnd n.c. refio gnd in7 zf7 gnd lo+ i.c. shdn out1- zf8 inc7 avdd out6+ gnd cw do vdd gnd gnd gnd out7- gnd gnd zf4 inc3 gnd gnd out7+ gnd avdd out8- gnd inc4 in4 out6- frame+ gnd in5 zf5 gnd sdio gnd gnd avdd zf6 inc5 gc- ovdd ovdd gnd inc8 in8 gnd clkin- ovdd gnd gnd gnd cs out5+ gnd gnd gnd v cc3 gnd gnd gnd gnd clkin+ gnd v cc3 gnd gnd out1+ gnd gnd gnd out8+ sclk out5- clkout+ gnd gnd gndgnd out2+ out2- gnd gnd gnd gnd gnd v ref v cc5 gnd gnd v cc5 v cc5 gc+ 123456789 10 11 12 123456789 10 11 12 v cc3 zf1 ci+ cq+ zf2 inc1 v cc5 cq- ci- inc2 in2 gnd gnd zf3 in3 gnd gnd in1 ab cd ef gh j k l m ab cd ef gh j k l m top view downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 18 maxim integrated bump description bump name function a1 in1 channel 1 input. connect to a 4.7nf coupling capacitor. a2 zf1 channel 1 active impedance matching line. ac-couple to in1 with a 2.2nf capacitor. a3, l6, m6 v cc3 3.3v power-supply voltage. bypass to gnd with a 0.1 f f capacitor as close as possible to the part. a4 ci+ 8-channel cw positive in-phase output. connect to 11v with a 120 i external resistor. a5 cq+ 8-channel cw positive quadrature output. connect to 11v with a 120 i external resistor. a6 lo+ positive cw local oscillator input. this clock is then divided in the beamformer. a7, b8, l7, m7 avdd 1.8v analog adc power-supply voltage. connect avdd to a 1.7v to 1.9v power supply. bypass avdd to gnd with a 0.1 f f capacitor as close as possible to the device. a8 n.c. no connection. internally not connected. a9 refio i/o reference (for internal calibration) a10 cwd vga/cw mode select. set cwd low to enable the vgas and disable the cw mixers. set cwd high to enable the cw mixers and disable the vgas. a11, c3?c10, d3?d10, e3?e10, f4?f9, g4?g9, h3?h10, j3?j10, k3?k10, l9, m9 gnd ground a12, f10, g10, m12 ovdd 1.8v digital adc power-supply voltage . bypass ovdd to gnd with a 0.1 f f capacitor as close as possible to the device. b1 zf2 channel 2 active impedance matching line. ac-couple to in2 with a 2.2nf capacitor. b2 inc1 channel 1 clamp input. connect to the source side of the coupling capacitor. b3, l3, m3, m4 v cc5 4.75v power-supply voltage. bypass to gnd with a 0.1 f f capacitor as close as possible to the device. b4 ci- 8-channel cw negative in-phase output. connect to 11v with a 120 i external resistor. b5 cq- 8-channel cw negative quadrature output. connect to 11v with a 120 i external resistor. b6 lo- negative cw local oscillator input b7 loon lo on control input. turns lo on starting on the next rising or falling edge of lo. b9 i.c. internally connected. leave unconnected. b10 shdn power-down (nap or sleep mode programmable through serial interface) b11 out1+ channel 1 positive lvds output b12 out1- channel 1 negative lvds output c1 inc2 channel 2 clamp input. connect to the source side of the coupling capacitor. c2 in2 channel 2 input. connect to a 4.7nf coupling capacitor. downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 19 maxim integrated bump description (continued) bump name function c11 out2+ channel 2 positive lvds output c12 out2- channel 2 negative lvds output d1 in3 channel 3 input. connect to a 4.7nf coupling capacitor. d2 zf3 channel 3 active impedance matching line. ac-couple to in3 with a 2.2nf capacitor. d11 out3+ channel 3 positive lvds output d12 out3- channel 3 negative lvds output e1 zf4 channel 4 active impedance matching line. ac-couple to in4 with a 2.2nf capacitor. e2 inc3 channel 3 clamp input. connect to the source side of the coupling capacitor. e11 out4+ channel 4 positive lvds output e12 out4- channel 4 negative lvds output f1 inc4 channel 4 clamp input. connect to the source side of the coupling capacitor. f2 in4 channel 4 input. connect to a 4.7nf coupling capacitor. f11 clkout+ positive lvds serial-clock output f12 clkout- negative lvds serial-clock output g1 in5 channel 5 input. connect to a 4.7nf coupling capacitor. g2 zf5 channel 5 active impedance matching line. ac-couple to in5 with a 2.2nf capacitor. g3, f3 ag analog ground for lna inputs. connect to a 47nf ac-coupling capacitor to ground. g11 frame+ positive frame-alignment lvds output g12 frame- negative frame-alignment lvds output h1 zf6 channel 6 active impedance matching line. ac-couple to in6 with a 2.2nf capacitor. h2 inc5 channel 5 clamp input. connect to the source side of the coupling capacitor. h11 out5+ channel 5 positive lvds output h12 out5- channel 5 negative lvds output j1 inc6 channel 6 clamp input. connect to the source side of the coupling capacitor. j2 in6 channel 6 input. connect to a 4.7nf coupling capacitor. j11 out6+ channel 6 positive lvds output j12 out6- channel 6 negative lvds output k1 in7 channel 7 input. connect to a 4.7nf coupling capacitor. k2 zf7 channel 7 active impedance matching line. ac-couple to in7 with a 2.2nf capacitor. k11 out7+ channel 7 positive lvds output k12 out7- channel 7 negative lvds output l1 zf8 channel 8 active impedance matching line. ac-couple to in8 with a 2.2nf capacitor. l2 inc7 channel 7 clamp input. connect to the source side of the coupling capacitor. l4 v ref voltage reference l5 gc- negative gain control voltage. set v gc+ - v gc- = +3v for maximum gain. set v gc+ - v gc- = -3v for minimum gain. downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 20 maxim integrated bump description (continued) bump name function l8 clkin+ positive differential adc clock input l10 sdio serial-data input l11 out8+ channel 8 positive lvds output l12 out8- channel 8 negative lvds output m1 in8 channel 8 input. connect to a 4.7nf coupling capacitor. m2 inc8 channel 8 clamp input. connect to the source side of the coupling capacitor. m5 gc+ positive gain control voltage. set v gc+ - v gc- = +3v for maximum gain. set v gc+ - v gc- = -3v for minimum gain. m8 clkin- negative differential adc clock input. connect to 0v for a single-ended clock. m10 sclk serial-clock input m11 cs chip select downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 21 maxim integrated functional diagram digital hpf 12-bit adc aaf frame+frame- pl l 6x1x clock circuitry serialize r digital hpf 12-bit adc vga lna out1+ frame- frame+ zf1 ci+ ci- cq+ cq- cwd sdio sclk loon cs lo+ lo- in1 in2 zf3zf4 in3in4 in5 in6 ag zf5zf6 zf7 zf2 out1-out2+ out2- out3- out4- out3+out4+ out5- out6+ out7+ out8+ out5+out6- out7- out8- lna serialize r digital hpf 12-bit adc vga lna serialize r digital hpf 12-bit adc vga lna serialize r digital hpf 12-bit adc vga lna serialize r digital hpf 12-bit adc vga lna serialize r digital hpf 12-bit adc vga lna serialize r digital hpf 12-bit adc vga vga lna serialize r in7 inc8 v cc5 v ref zf8 in8 v cc3 gc+ gc- gnd shdn gnd dout ovdd avdd gnd clkout+ clkout- clkin+ clkin- inc7 inc2inc3 inc4 inc1 inc5 inc6 MAX2079 aaf aaf aaf aaf aaf aafaaf downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 22 maxim integrated detailed description modes of operation the device requires programming before it can be used. the operating modes are controlled by 17 8-bit registers (00h to 10h). table 3 shows the functions of these pro - gramming registers. low-noise amplifier (lna) each of the device?s lnas is optimized for excellent dynamic range and linearity performance characteristics, making it ideal for ultrasound imaging applications. when the lna is placed in low-gain mode, the input resistance (r in ), being a function of the gain a (r in = r f /(1 + a)), increases by a factor of approximately 2. consequently, the switches that control the feedback resistance (r fb ) have to be changed. for instance, the 100 i mode in high gain becomes the 200 i mode in low gain (see table 30 ). variable-gain amplifier (vga) the device?s vgas are optimized for high linearity, high dynamic range, and low output-noise performance, all of which are critical parameters for ultrasound imaging applications. each vga path includes circuitry for adjust - ing analog gain, as well as an output buffer with differ - ential output ports that drive the aaf and adc. the vga gain can be adjusted through the differential gain-control input (gc+ and gc-). set the differential gain control input voltage at -3v for minimum gain and +3v for maxi - mum gain. the differential analog control common-mode voltage is 1.65v (typ). overload recovery the device is also optimized for quick overload recovery for operation under the large input-signal conditions that are typically found in ultrasound input-buffer imaging applications. see the typical operating characteristics for an illustration of the rapid recovery time from a transmit-related overload. dynamic offsets or dc offsets in the device can be removed by enabling the digital hpf function contained within the adc. the unique structure of the digital hpf allows for the removal of up to q 117mv of dynamic or static dc offset, without reducing the dynamic range of the adc. octal continuous-wave (cw) mixer the device cw mixers are designed using an active double-balanced topology. the mixers achieve high dynamic range and high-linearity performance, with exceptionally low thermal and jitter noise, ideal for ultra - sound cwd signal reception.the octal array exhibits quadrature and in-phase dif - ferential current outputs (cq+, cq-, ci+, ci-) to pro - duce the total cwd beamformed signal. the maximum differential current output is typically 3ma p-p and the mixer output-compliance voltage ranges from 4.5v to 12v.each mixer can be programmed to 1 of 16 phases; there - fore, 4 bits are required for each channel for programming.each cw channel can be programmed to an off state by setting bit cw_shdn_chn to 1. the power-down mode (shdn) line overrides this soft shutdown. after the serial shift registers have been programmed, the cs signal, when going high, loads the phase informa - tion in the form of 5 bits per channel into the i/q phase divider/selectors. this presets the dividers, selecting the appropriate mixer phasing. see table 40 for mixer phase configurations. cw mixer output summation the outputs from the octal-channel mixer array are summed internally to produce the total cwd summed beamformed signal. the octal array produces eight differential quadrature (q) outputs and eight differential in-phase (i) outputs. all quadrature and in-phase outputs are summed into single i and q differential current out - puts (cq+, cq-, ci+, ci-). cwd beamforming is achieved using a single 8 x lo high-frequency master clock that is divided down to the cwd frequency using internal dividers. the beamformer provides /16 resolution with an 8 x lo clock using both edges of the clock, assuming a 50% duty cycle. an eas - ily available low-phase-noise 200mhz master clock can therefore be used to generate the necessary cwd fre - quencies with adequate resolution. lo phase select the lo phase dividers can be programmed through the shift registers to allow for 16 quadrature phases for a complete cw beamforming solution. downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 23 maxim integrated figure 1. cwd analog front-end beamformer simplified block diagram vga and cw mixer operation during normal operation, the device is configured so that either the vga path is enabled while the mixer array is powered down (vga mode), or the quadrature mixer array is enabled while the vga path is powered down (cw mode). for vga mode, set cwd to a logic-high, and for cw mode, set cwd to a logic-low. external voltage reference connect an external, low-noise, +2.5v reference to the v ref pin. bypass v ref to ground with a 0.1 f f capaci - tor as close as possible to the device. the device noise performance is dependent on the external noise at v ref . adc clock input the input clock interface provides for flexibility in the requirements of the clock driver. the device accepts a fully differential clock or single-ended logic-level clock. the device is specified for an input sampling 25mhz to 50mhz frequency range. by default, the internal phase-locked loop (pll) is configured to accept input clock frequencies from 39mhz to 50mhz. the pll is programmed through the pll sampling rate register (00h, table 4 ). table 5 details the complete range of pll sampling frequency settings.for differential clock operation, connect a differential clock to the clkin+ and clkin- inputs. the input iq channel 1 i/ q phase divider / se lector 5 loon lo- lo+ cwq cwi clk din ld channel 2 i/ q phase divider / se lector channel 3 i/ q phase divider / se lector channel 4 i/ q phase divider / se lector channel 5 i/ q phas e divider / se lector channel 6 i/ q phas e divider / se lector channel 7 i/ q phase divider / se lector channel 8 i/ q phas e divide r/ se lector iq iq iq iq iq iq iq 5 5 5 5 5 5 5 MAX2079 control cwd programming shift register downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 24 maxim integrated figure 2. cwd output beamforming example common mode is established internally to allow for ac-coupling. the self-biased input common-mode volt - age defaults to 1.2v. the differential clock signal can also be dc-coupled if the externally established com - mon-mode voltage is constrained to the specified clock input common-mode range of 1v to 1.4v. a differential input termination of 100 i can be switched in by pro - gramming the clkin control register (04h[4], table 19 ). for single-ended operation, connect clkin- to gnd and drive the clkin+ input with a logic-level signal. when the clkin- input is grounded (or pulled below the threshold of the clock-mode detection comparator), the differential-to-single-ended conversion stage is disabled and the logic-level inverter path is activated. the input common-mode self-bias is disconnected from clkin+, and provides a weak pullup bias to avdd for clkin- during single-ended clock operation. figure 3. digital highpass filter cw_iout+cw_iout- cw_qout- cw_qout+ +v+v lo divider to i channel cwd adc to q channel cwd adc cwd i channels in cwd q channels in cwd i/q lo (bypass) hpf1control bits r1 t hpf1 [3:0] t (bypass) hpf2 r2 t hpf2 [3:0] t g1 atten [1:0] downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 25 maxim integrated figure 4. simplified clock input schematic power-down and low-power mode the device can also be powered down with the shdn pin. set shdn to +1.8v to place the device in power- down mode. in power-down mode, the device draws a total supply current less than 1 f a from the 5v and 3.3v supplies, and less than 0.4ma from the 1.8v supplies. set shdn to logic-low for normal operation. a low-power mode is available to lower the required power for cwd operation. when selected, the complex mixers operate at lower quiescent currents. note that operation in this mode slightly reduces the dynamic per - formance of the device. table 6 shows the logic function of the standard operating modes. in addition to power-down mode, the device can be placed into a reduced-power standby or nap mode, which allows for rapid power-up in vga mode. nap mode is accessable by setting the shdn pin to +1.8v, with the adc_nap_shdn1 and afe_nap_shdn1 registers set to 1 (see table 6 ). nap mode is not meant to be used in conjunction with cwd mode; valid cwd power states are normal cwd low-power and power-down modes. although no device damage occurs, programming the device for nap mode and setting the shdn pin high can create invalid signal outputs in cwd mode. clkin+ select threshold avdd 10k i 20k i 5k i 5k i 50 i 50 i clkin- input common-mode self-bias block clkin_internal 10 0 i termination, programmed: 04h[4] differential-to-single-ende d clock conversion single-ended clock mode: inverter path select 2:1 mux differential mode: clkin- > select threshol d single-ended mode: clkin- < select threshold downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 26 maxim integrated programmable, digital highpass 2-pole filter digital highpass filter characteristics this digital hpf is implemented as the cascade of two identical first-order highpass iir filter sections. each section implements the difference equation: y[n] r y[n - 1] x[n] - x[n - 1] = + where x[n] is the input and y[n] is the output. the highpass 3db corner frequency is established by the filter coefficient (r). each section can be independently programmed to one of 10 possible values or placed into bypass mode. the available filter coefficient values and corresponding cutoff frequency are given in table 1 . table 1. digital filter cutoff-frequency setting filter coefficient (r) 3db cutoff frequency (f s /2) 3db cutoff frequency mhz (f s = 50msps) one-filter sections 54/64 0.843750 0.046294 1.157 55/64 0.859375 0.041943 1.049 56/64 0.875000 0.037535 0.938 57/64 0.890625 0.033069 0.827 58/64 0.906250 0.028544 0.714 59/64 0.921875 0.023956 0.599 60/64 0.937500 0.019303 0.483 61/64 0.953125 0.014584 0.365 62/64 0.968750 0.009796 0.245 63/64 0.984375 0.004935 0.123 two-filter sections 54/64 0.843750 0.069441 1.736 55/64 0.859375 0.062915 1.573 56/64 0.875000 0.056303 1.408 57/64 0.890625 0.049604 1.240 58/64 0.906250 0.042816 1.070 59/64 0.921875 0.035934 0.898 60/64 0.937500 0.028955 0.724 61/64 0.953125 0.021876 0.547 62/64 0.968750 0.014694 0.367 63/64 0.984375 0.007403 0.185 downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 27 maxim integrated figure 5. digital hpf magnitude frequency response (1 stage)figure 7. digital hpf phase frequency response (1 stage) figure 7a. digital hpf group-delay frequency response (1 stage) figure 6. digital hpf magnitude frequency response (1 stage) frequency (normalized f s /2) response (db) 10 -1 10 -2 10 -3 10 -0 digital hpf magnitude frequency response (1 stage) -40 -30 -20 -10 0 10 -50 r1 = 63/64 r1 = 54/64 digital hpf phase frequency response (1 stage) frequency (normalized f s /2) phase ( ) 10 -1 10 -2 20 40 60 80 100 120 140 160 180 0 10 -3 10 -0 r1 = 54/64 r1 = 63/64 digital hpf magnitude frequency response (1 stage) frequency (normalized f s /2) response (db) 10 -1 10 -2 -6 -5 -4 -3 -2 -1 0 1 2 3 -7 10 -3 10 0 digital hpf group-delay frequency response (1 stage) frequency (normalized f s /2) delay (samples) 10 -1 10 -2 1 2 3 4 5 6 7 8 9 10 0 10 -3 10 0 r1 = 54/64 r1 = 63/64 downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 28 maxim integrated figure 8. digital hpf impulse-time response (1 stage) figure 10. digital hpf magnitude-frequency response (2 stage) figure 9. digital hpf impulse-time response (1 stage)figure 11. digital hpf magnitude-frequency response (2 stage) digital hpf impulse-time response (1 stage) time (samples) response 160 140 02 04 08 0 100 60 120 -0.2 0 0.2 0.4 0.6 0.8 1.0 -0.4 -20 180 digital hpf impulse-time response (1 stage) time (samples) response 45 40 30 35 10 15 20 25 5 -0.25 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 05 0 r1 = 63/64 r1 = 54/64 frequency (normalized f s /2) response (db) 10 -1 10 -2 10 -3 10 0 digital hpf magnitude-frequency response (2 stage) -40 -30 -20 -10 0 10 -50 r1 = 63/64 r1 = 54/64 digital hpf magnitude-frequency response (2 stage) frequency (normalized f s /2) response (db) 10 -1 10 -2 -6 -5 -4 -3 -2 -1 0 1 2 3 -7 10 -3 10 0 downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 29 maxim integrated figure 12. digital hpf phase frequency response (2 stage)figure 14. digital hpf impulse-time response (2 stage) figure 13. digital hpf group-delay frequency response (2 stage)figure 15. digital hpf impulse-time response (2 stage) digital hpf phase frequency response (2 stage) frequency (normalized f s /2) phase (degrees) 10 -1 10 -2 20 40 60 80 100 120 140 160 180 0 10 -3 10 0 r1 = 54/64 r1 = 63/64 digital hpf impulse-time response (2 stage) time (samples) response 45 40 30 35 10 15 20 25 5 -0.25 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 05 0 r1 = r2 = 54/64 r1 = r2 = 63/64 digital hpf group-delay frequency response (2 stage) frequency (normalized f s /2) delay (samples) 10 -1 10 -2 1 2 3 4 5 6 7 8 9 10 0 10 -3 10 0 r1 = r2 = 54/64 r1 = r2 = 63/64 digital hpf impulse-time response (2 stage) time (samples) response 140 120 02 04 08 0 60 100 -0.2 0 0.2 0.4 0.6 0.8 1.0 -0.4 -20 180 160 downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 30 maxim integrated the digital hpf provides a small-signal gain that depends on the filter coefficient. this effectively reduces slightly the full-scale input range of the adc. a plot of filter gain vs. filter coefficient is shown in figure 16 . a coarse digital multiplier is incorporated at the output of the filter to pro - vide partial compensation of the digital filter gain. table 2 provides the recommended gain-compensation settings for different filter cutoff-frequency settings. figure 16. digital hpf gain vs. filter coefficienttable 2. gain-compensation settings for different filter cutoff-frequency settings * parts are factory trimmed with this setting. programming can be changed. r filter mode poles f 3db (f s /2) gain gain (db) gain comp (db) overall gain (db) n/a bypass n/a n/a 1 0 0 0 63/64 filter 1 0.004935 1 0.0681 0 0.0681 62/64 filter 1 0.009796 1 0.1368 0 0.1368 61/64 filter 1 0.014584 1 0.206 0 0.206 60/64 filter 1 0.019303 1 0.2758 0 0.2758 59/64 filter 1 0.023956 1 0.3461 0 0.3461 58/64 filter 1 0.028544 15/16 0.417 -0.5606 -0.1436 57/64 filter 1 0.033069 15/16 0.4885 -0.5606 -0.0721 56/64 filter 1 0.037535 15/16 0.5606 -0.5606 0 55/64 filter 1 0.041943 15/16 0.6333 -0.5606 0.0727 54/64 filter 1 0.046294 15/16 0.7066 -0.5606 0.146 63/64 filter 2 0.007403 1 0.1362 0 0.1362 62/64 filter 2 0.014694 1 0.2736 0 0.2736 61/64 filter 2 0.021876 15/16 0.412 -0.5606 -0.1486 60/64* filter 2 0.028955 15/16 0.5515 -0.5606 -0.0091 59/64 filter 2 0.035934 15/16 0.6922 -0.5606 0.1316 58/64 filter 2 0.042816 15/16 0.834 -0.5606 0.2734 57/64 filter 2 0.049604 7/8 0.977 -1.1598 -0.1828 56/64 filter 2 0.056303 7/8 1.1211 -1.1598 -0.0387 55/64 filter 2 0.062915 7/8 1.2665 -1.1598 0.1067 54/64 filter 2 0.069441 7/8 1.4131 -1.1598 0.2533 digital hpf gain vs. filter coefficient filter coefficient (/64) gain (db) 62 60 58 56 54 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 52 64 + + + + + + + + + ++ + + + + + + + + + 2-stage iir 1-stage iir downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 31 maxim integrated system timing requirements figure 17 shows the relationship between the analog inputs, input clock, frame-alignment output, serial-clock output, and serial-data outputs. the differential adc input signal is sampled on the rising edge of the applied clock signal (clkin+, clkin-), and the result ing data appears at the digital outputs 10.5 clock cycles later. figure 18 provides a detailed, two-conversion timing diagram of the relationship between inputs and outputs. figure 17. adc timing (overall)figure 18. adc timing (detail) in_+ - in_- clkin+ - clkin- clkout+ - clkout- out_+ - out_- frame+ - frame- t sample n - 10 n - 9n - 8n - 7n - 6n - 5n - 4n - 3n - 2n - 1n output data frame n n + 1 n + 2 n + 3n + 4n + 5 10.5 clock-cycle data latency n + 6n + 7n + 8 n + 9 n + 10 t sample t sf t df n n + 1 d7 n-9 d0 n-8 d1 1 n- 9 d1 0 n- 9 d1 n-8 d2 n-8 d3 n-8 d4 n-8 d5 n-8 d6 n-8 d7 n-8 d8 n-8 d9 n-8 d10 n-8 d11 n-8 d9 n-9 d8 n-9 d0 n-7 d1 n-9 d2 n-9 d3 n-9 d4 n-9 d5 n-9 d6 n-9 in_+ - in_- clkin+ - clkin- clkout+ - clkout- out_+ - out_- frame+ - frame- t sample ?sample period t df ?frame_ rise to clkout_ rise t sf ?sample clkin_ rise to frame rise downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 32 maxim integrated clock output (clkout+, clkout-) the adc provides a differential clock output that con sists of clkout+ and clkout-. as shown in figure 19 , the serial-output data is clocked out of the device on both edges of the clock output. the frequency of the output clock is six times (6x) the frequency of the input clock. the output data format and test pattern/digital hpf select register (01h) allows the phase of the clock output to be adjusted relative to the output data frame ( table 7 , figure 21 ). frame-alignment output (frame+, frame-) the adc provides a differential frame-alignment signal that consists of frame+ and frame-. as shown in figure 18 , the rising edge of the frame-alignment signal corresponds to the first bit (d0) of the 12-bit serial-data stream. the frequency of the frame-alignment signal is identical to the frequency of the input clock; however, the duty cycle varies depending on the input clock frequency. serial-output data (out_+, out_-) the adc provides conversion results through individual differential outputs consisting of out_+ and out_-. the results are valid 10.5 input clock cycles after a sample is taken. as shown in figure 19 , the output data is clocked out on both edges of the output clock, lsb (d0) first (by default). figure 18 displays the detailed serial-output timing diagram. differential lvds digital outputs the adc features programmable, fully differential lvds digital outputs. by default, the 12-bit data output is trans - mitted lsb first, in offset binary format. the output data format and test pattern/digital hpf select register (01h, table 7 ) allows customization of the output bit order and data format. the output bit order can be reconfigured to transmit msb first, and the output data format can be changed to two?s complement. table 8 contains full out - put data configuration details. the lvds outputs feature flexible programming options. first, the output common-mode voltage can be pro - grammed from 0.6v to 1.2v (default) in 200mv steps ( table 15 ). use the lvds output driver level register (02h, table 11 ) to adjust the output common-mode voltage. the lvds output driver current is also fully programma - ble through the lvds output driver management register (03h, table 16 ). by default, the output driver current is set to 3.5ma. the output driver current can be adjusted from 0.5ma to 7.5ma in 0.5ma steps ( table 17 ). the lvds output drivers also feature optional internal terminations that can be enabled and adjusted by the lvds output driver management register (03h, table 16 ). by default, the internal output driver termination is dis - abled. see table 18 for all possible configurations. output driver level tests the lvds outputs (data, clock, and frame) can be configured to static logic-level test states through the lvds output driver level register (02h, table 11 ). the complete list of settings for the static logic-level test states can be found in tables 12 , 13 , and 14 . data output test patterns the lvds data outputs can be configured to output several different, recognizable test patterns. test patterns are enabled and selected using the output data format and test pattern/digital hpf select register (01h, table 7 ). a complete list of test pattern options are listed in table 9 , and custom test pattern details can be found in the custom test pattern registers (07h, 08h, 09h) section (including tables 24 , 27 , and 28 ). power management the shdn input is used to toggle between two power-management states. power state 0 corresponds to shdn = 0, while power state 1 corresponds to shdn = 1. the pll sampling rate and power management register (00h) and the channel power management registers (05h and 06h) fully define each power-management state. by default, shdn = 1 shuts down the device, and shdn = 0 returns the adcs to full-power operation. use of the shdn input is not required for power management. for either state of shdn, complete power-manage- ment flexibility is provided, including individual adc channel power-management control, as well as the option of which reduced power-mode to utilize in each power state. the reduced-power modes available are figure 19. serial output detailed timing diagram t od t ch t od d0 d1 d2 d3 d4 t cl clkout+ - clkout- out_+ - out_- t ch ?clkout_ output- width high t cl ?clkout_ output- width low t od ?data valid to clkout_ ris e/ fall downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 33 maxim integrated sleep mode and nap mode. the device cannot enter either of these states unless no adc channels are active in the current power state ( table 6 ). in nap mode, the reference, duty-cycle equalizer, and clock-multiplier pll circuits remain active for rapid wake- up time. in nap mode, the externally applied clock signal must remain active for the duty-cycle equalizer and pll to remain locked. typical wake-up time from nap mode is 2 f s. in sleep mode, all circuits are turned off except for the bandgap voltage-generation circuit. all registers retain previously programmed values during sleep mode. typical wake-up time from sleep mode is 2ms (typ). power-on and reset the user-programmable register default settings and other factory-programmed settings are stored in a non - volatile memory. upon device power-up, these values are loaded into the control registers. the operation occurs after the application of a valid supply voltage to avdd and ovdd, and the presence of an input clock signal. the user-programmed register values are retained as long as the avdd and ovdd voltages are applied. a reset condition overwrites all user-programmed regis - ters with the factory-default values. the reset condition occurs on power-up and can be initiated while powered with a software write command (write 5ah) through the serial-port interface to the special function register (10h). the reset time is proportional to the adc clock period and requires 415 f s at 50msps. power-down and low-power (nap) mode and channel selection the shdn pin is a toggle switch between any two power- management states. in most cases, the shdn = 0 state is on, and the shdn = 1 state is off. however, complete flexibility is provided, allowing the user to toggle between active and nap, active and sleep, etc. nap mode is defined as a reduced-power state with rapid wake-up time on the order of 2 f s. sleep mode is a very-low-power mode (~1mw) with a much longer wake-up time on the order of 2ms. the serial port and programmable registers remain active during nap and sleep modes. chn_on_shdn0 n = [1:8] 1 channel n is on when the shdn pin is low. 0 channel n is off when the shdn pin is low. chn_on_shdn1 n = [1:8] 1 channel n is on when the shdn pin is high. 0 channel n is off when the shdn pin is high. adc_nap_shdn0 1 adc in nap mode when all channels are off, or the cwd pin is high and the shdn pin is low. 0 adc in sleep mode when all channels are off, or the cwd pin is high and the shdn pin is low. adc_nap_shdn1 1 adc in nap mode when all channels are off, or the cwd pin is high and the shdn pin is high. 0 adc in sleep mode when all channels are off, or the cwd pin is high and the shdn pin is high. afe_nap_shdn0 1 afe in nap mode when all channels are off and the shdn pin is low. 0 afe in sleep mode when all channels are off and the shdn pin is low. afe_nap_shdn1 1 afe in nap mode when all channels are off and the shdn pin is high. 0 afe in sleep mode when all channels are off and the shdn pin is high. 3-wire serial peripheral interface (spi) the adc operates as a slave device that sends and receives data through a 3-wire spi interface. a mas - ter device must initiate all data transfers to and from the device. the device uses an active-low spi chip- select input ( cs ) to enable communication with timing controlled through the externally generated spl clock input (sclk). all data is sent and received through the bidirectional spi data line (sdio). the device has 16 user-programmable control registers and one special- function register, which are accessed and programmed through this interface. spi communication format figure 20 shows an adc spi communication cycle. all spi communication cycles are made up of 2 bytes of data on sdio and require 16 clock cycles on sclk to be completed. to initiate an spi read or write commu - nication cycle, cs must first transition from a logic-high to a logic-low state. while cs remains low, serial data is clocked in from sdio on rising edges of sclk, and clocked out (for a read) on the falling edges of sclk. when cs is high, the device does not respond to sclk transitions, and no data is read from or written to sdio. cs must transition back to logic-high after each read/ write cycle is completed. downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 34 maxim integrated figure 20. spi timing diagram the first byte transmitted on sdio is always provided by the master. the adc (slave device) clocks in the data from sdio on each rising edge of sclk. the first bit received selects whether the communication cycle is a read or a write. logic 1 selects a read cycle, while logic 0 selects a write cycle. the next 7 bits (msb first) are the register address for the read or write cycle. the address can indicate any of the 16 user-programmable control registers (00h to 0fh), or the special-function register (10h, write only). attempting to read/write with any other address has no effect ( table 3 ). the second byte on sdio is sent to the adc in the case of a write, or received from the adc in the case of a read. for a write command, the device continues to clock in the data on sdio on each rising edge of sclk. in the case of a read command, the device writes data to sdio on each falling edge of sclk. the data byte is transmitted and received msb first in both cases. the detailed spi timing requirements are shown in figure 20 . t css t csh t sclk t sds t sdh t sdd cs sclk sdio cs sclk sdio r/ wa 6a5a 4a 3a 2a 1a 0d 7d 6d 5d 4d 3d 2d1d 0 write address data write or read read t scl k ?sclk period t css ?sclk-to-cs setup time t csh ?sclk-to-cs hold time t sds ? sdio-to-sclk setup time t sdh ?sdio-to-sclk hold time t sdd ?sclk-to-sdio output data delay r / w 0 = wr ite 1 = read downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 35 maxim integrated table 3. user-programmable adc control registerstable 4. pll sampling rate and power management (00h) x = don?t care. table 5. pll frequency-control settings (00h[6:4]) address read/write por state function 00h r/w 0001-0001 pll sampling rate and power management 01h r/w 0000-0000 output data format and test pattern/digital hpf select 02h r/w 0000-0000 lvds output driver level 03h r/w 0000-0000 lvds output driver management 04h r/w 0000-0000 adc clkin control 05h r/w 1111-1111 channel power management: shdn0 06h r/w 0000-0000 channel power management: shdn1 07h r/w 0100-0100 digital hpf 1 and 2 -3db cutoff/custom test patterns 1 08h r/w 0101-0110 digital hpf 1 and attentuation/custom test patterns 2 09h r/w 0101-1010 custom test patterns 2 and 1 (4msbs) 0ah r/w 0101-1100 afe settings 0bh r/w 0000-0000 cw beamformer 1 0ch r/w 0000-0000 cw beamformer 2 0dh r/w 0000-0000 cw beamformer 3 0eh r/w 0000-0000 cw beamformer 4 0fh r/w 0000-0000 cw beamformer 5 10h r/w n/a special function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? pll[2:0] afe_nap_shdn1 afe_nap_shdn0 adc_nap_shdn1 adc_nap_shdn0 clock multiplier setting minimum sampling frequency (mhz) maximum sampling frequency (mhz) pll[2] pll[1] pll[0] 0 0 0 not used 0 0 1 39 50 0 1 0 28.5 39 0 1 1 25 28.8 1 x x not used downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 36 maxim integrated x = don?t care. table 6. power-management programming pins registers description shdn cwd chn_on_shdn0 n = [1:8] chn_on_shdn1 n = [1:8] adc_nap_shdn0adc_nap_shdn1 afe_nap_shdn0afe_nap_shdn1 default register modes 0 0 11111111 00000000 0 1 0 1 8 channels active (vga mode) 0 1 11111111 00000000 0 1 0 1 cw doppler mode (adc in nap mode) 1 0 11111111 00000000 0 1 0 1 nap mode (adc and afe) 1 1 11111111 00000000 0 1 0 1 cw doppler mode (adc in nap mode) programmed register modes 0 0 1xxxxxxxx1xxxxxx xx1xxxxx xxx1xxxx xxxx1xxx xxxxx1xx xxxxxx1x xxxxxxx1 xxxxxxxx x x x x 1 or more channels active (vga mode) 0 0 00000000 xxxxxxxx 0 x 0 x sleep mode (adc and afe) 0 0 00000000 xxxxxxxx 0 x 1 x adc sleep/afe nap 0 0 00000000 xxxxxxxx 1 x 0 x adc nap/afe sleep 0 0 00000000 xxxxxxxx 1 x 1 x nap mode (adc and afe) 0 1 xxxxxxxx xxxxxxxx 0 x x x cw doppler mode (adc in sleep mode) 0 1 xxxxxxxx xxxxxxxx 1 x x x cw doppler mode (adc in nap mode) 1 0 xxxxxxxx 1xxxxxxxx1xxxxxx xx1xxxxx xxx1xxxx xxxx1xxx xxxxx1xx xxxxxx1x xxxxxxx1 x x x x 1 or more channels active (vga mode) 1 0 xxxxxxxx 00000000 x 0 x 0 sleep mode (adc and afe) 1 0 xxxxxxxx 00000000 x 0 x 1 adc sleep/afe nap 1 0 xxxxxxxx 00000000 x 1 x 0 adc nap/afe sleep 1 0 xxxxxxxx 00000000 x 1 x 1 nap mode (adc and afe) 1 1 xxxxxxxx xxxxxxxx x 0 x x cw doppler mode (adc in sleep mode) 1 1 xxxxxxxx xxxxxxxx x 1 x x cw doppler mode (adc in nap mode) downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 37 maxim integrated table 7. output data format and test pattern/digital hpf select (01h)table 8. lvds output data format programming figure 21. output clock phase bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 test_pattern[2:0] test_data clkout_phase[1:0] data_format bit_order data_format bit_order lvds output data format 0 0 binary, lsb first (default) 0 1 binary, msb first 1 0 two?s complement, lsb first 1 1 two?s complement, msb first clkoutclkout datadata d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 frame clkout datadata frame clkout frame frame clkout_phase [1:0] = 00 (default) clkout_phase [1:0] = 10 clkout_phase [1:0] = 01 clkout_phase [1:0] = 11 d0 d1 d2 d3 downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 38 maxim integrated table 9. test pattern programming and digital highpass filter selectiontable 10. pseudorandom data test pattern (when custom test pattern is selected (test_pattern[2:0] = 100) the output is a short (2 9 ) pn sequence. a long (2 23 ) sequence output is provided when test_pattern[2:0] = 101.) x = don?t care. x = don?t care. table 11. lvds output driver level (02h)table 12. test data (out_) level programming table 13. test clkout_ level programming x = don?t care. custom test pattern when custom test pattern is selected (test_pattern[2:0] = 010), the output alternates between bits_custom1[11:0] and bits_custom2[11:0]. if a single repeating word is desired, program bits_custom2[11:0] to the same value as bits_custom1[11:0]. test_data test_pattern[2:0] test pattern format 0 x x x disabled, normal operation with digital hpf selected (default) 1 0 0 0 data skew (010101010101), repeats every frame 1 0 0 1 data sync (111111000000), repeats every frame 1 0 1 0 custom test pattern, repeats every 2 frames 1 0 1 1 ramping pattern from 0 to 4095 (repeats) 1 1 0 0 pseudorandom data pattern, short sequence (2 9 ) 1 1 0 1 pseudorandom data pattern, long sequence (2 23 ) 1 1 1 0 not used 1 1 1 1 not used sequence initial value first 3 samples short (2 9 ) 0x0df 0xdf9, 0x353, 0x301 long (2 23 ) 0x29b80a 0x591, 0xfd7, 0x0a3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lvds_cm[1:0] test_frame_level[1:0] test_clkout_level[1:0] test_data_level[1:0] test_data_level[1:0] data (out_) output x 0 normal data output 0 1 output low (static) 1 1 output high (static) test_clkout_level[1:0] clkout_ output x 0 normal clkout_ output 0 1 output low (static) 1 1 output high (static) downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 39 maxim integrated table 14. test frame level programming table 16. lvds output driver management (03h) table 17. lvds output drive current configuration (selectable lvds drive current fully selectable from 0.5ma to 7.5ma in 0.5ma increments (3.5ma default). supports ansi-644 and ieee 1596.3.) table 15. lvds output common-mode voltage adjustment x = don?t care. test_frame_level[1:0] frame output x 0 normal frame output 0 1 output low (static) 1 1 output high (static) lvds_cm[1:0] lvds output common- mode voltage (v) 0 0 1.2 (default) 0 1 1.0 1 0 0.8 1 1 0.6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? lvds_term[2:0] lvds_iadj[3:0] lvds_iadj[3:0] lvds current (ma) 0 0 0 0 3.5ma, 350mv at 100 i (default) 0 0 0 1 0.5 0 0 1 0 1.0 0 0 1 1 1.5 0 1 0 0 2.0 0 1 0 1 2.5 0 1 1 0 3.0 0 1 1 1 3.5 1 0 0 0 4.0 1 0 0 1 4.5 1 0 1 0 5.0 1 0 1 1 5.5 1 1 0 0 6.0 1 1 0 1 6.5 1 1 1 0 7.0 1 1 1 1 7.5 downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 40 maxim integrated table 21. channel power management: shdn1 (06h)table 22. digital highpass filter control coefficients (07h; if test_data 01[4] = 0) table 19. clkin termination control (04h)table 20. channel power management: shdn0 (05h) table 18. lvds output driver internal termination configuration bit 0 always program this bit to 0. clock input termination clkin_term = 0: 100 i not selected. clkin_term = 1: switches in 100 i across differential clock inputs. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ch8_shdn1 ch7_shdn1 ch6_shdn1 ch5_shdn1 ch4_shdn1 ch3_shdn1 ch2_shdn1 ch1_shdn1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hpf2[3:0] hpf1[3:0] lvds_term[2:0] lvds internal termination ( i ) 0 0 0 ? 0 0 1 800 0 1 0 400 0 1 1 267 1 0 0 200 1 0 1 160 1 1 0 133 1 1 1 100 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ? ? clkin_term ? ? ? 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ch8_shdn0 ch7_shdn0 ch6_shdn0 ch5_shdn0 ch4_shdn0 ch3_shdn0 ch2_shdn0 ch1_shdn0 downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 41 maxim integrated table 23. digital highpass filter configurationtable 24. custom test pattern 1 (07h; if test_data 01[4] = 1) table 25. digital highpass filter attenuation (08h; if test_data 01[4] = 0) table 26. digital highpass filter attenuation hpf1[3:0], hpf2[3:0] r1/r2 filter mode 0 0 0 0 n/a bypass 0 0 0 1 63/64 filter; f 3db = 0.004935, f s /2 0 0 1 0 62/64 filter; f 3db = 0.009796, f s /2 0 0 1 1 61/64 filter; f 3db = 0.014584, f s /2 0 1 0 0 60/64 filter; f 3db = 0.019303, f s /2 0 1 0 1 59/64 filter; f 3db = 0.023956, f s /2 0 1 1 0 58/64 filter; f 3db = 0.028544, f s /2 0 1 1 1 57/64 filter; f 3db = 0.033069, f s /2 1 0 0 0 56/64 filter; f 3db = 0.037535, f s /2 1 0 0 1 55/64 filter; f 3db = 0.041943, f s /2 1 0 1 0 54/64 filter; f 3db = 0.046294, f s /2 1 0 1 1 n/a bypass 1 1 0 0 n/a bypass 1 1 0 1 n/a bypass 1 1 1 0 n/a bypass 1 1 1 1 n/a bypass bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bits_custom1[7:0] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ? ? ? ? ? atten[1:0] atten[1:0] gain gain (db) 0 0 1 0 0 1 1 0 1 0 15/16 -0.58 1 1 7/8 -1.16 downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 42 maxim integrated table 31. afe filter bandwidth control table 27. custom test pattern 2 (08h; if test_data 01[4] = 1)table 28. custom test pattern 3 (09h) table 29. afe settings (0ah) table 30. afe input impedance and lna gain control x = don?t care. afe_bw[0:1] bandwidth (mhz) 0 0 9 0 1 10 1 0 15 1 1 18 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bits_custom2[7:0] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bits_custom2[11:8] bits_custom1[11:8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 afe_rin[0:2] afe_lna_gain afe_bw[0:1] cwd_power_mode afe_oclamp afe_lna_gain afe_rin[0:2] input resistance ( i ) lna gain (db) 0 0 0 0 100 12.5 0 1 0 0 200 12.5 0 0 1 0 400 12.5 0 1 1 0 2000 12.5 0 x x 1 external r 12.5 1 0 0 0 50 18.5 1 1 0 0 100 18.5 1 0 1 0 200 18.5 1 1 1 0 1000 18.5 1 x x 1 external r 18.5 downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 43 maxim integrated table 34. cw beamformer 1 (0bh)table 35. cw beamformer 2 (0ch) table 36. cw beamformer 3 (0dh) table 37. cw beamformer 4 (0eh) table 38. cw beamformer 5 (0fh) table 32. cwd power mode table 33. vga output clamp control cwd_power_mode cwd power mode 0 full power (default, nominal) 1 low power afe_oclamp vga output clamp 0 no clamp (default, nominal) 1 clamp active bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cw_phase_ch2[1:3] cw_shdn_ch1 cw_phase_ch1[0:3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cw_phase_ch4[3] cw_shdn_ch3 cw_phase_ch3[0:3] cw_shdn_ch2 cw_phase_ch2[0] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cw_phase_ch5[0:3] cw_shdn_ch4 cw_phase_ch4[0:2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cw_phase_ch7[2:3] cw_shdn_ch6 cw_phase_ch6[0:3] cw_shdn_ch5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cw_shdn_ch8 cw_phase_ch8[0:3] cw_shdn_ch7 cw_phase_ch7[0:1] downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 44 maxim integrated cw doppler mode control cw_shdn_chn is set to 0 in normal operation (default). set it to 1 for power-down channel n when in cw doppler mode. note: the transfer data to afe procedure described in the afe programming and data transfer section should be performed twice when setting any cw_shdn_chn bits from 0 to 1 to enable a cw doppler channel(s). this procedure only applies to the cw_shdn_chn bits; all other bits are transferred to the afe in a single operation. table 39. degree change by each phase bittable 40. phase rotation table 41. special function register (10h) ph[0] ph[1] ph[2] ph[3] phase -22.5 -180 -90 -45 degrees cw_phase_chn[0:3] phase (degrees) -22.5 -180 -90 -45 0 0 0 0 0 1 0 0 0 337.5 0 1 0 0 180 1 1 0 0 157.5 0 0 1 0 270 1 0 1 0 247.5 0 1 1 0 90 1 1 1 0 67.5 0 0 0 1 315 1 0 0 1 292.5 0 1 0 1 135 1 1 0 1 112.5 0 0 1 1 225 1 0 1 1 202.5 0 1 1 1 45 1 1 1 1 22.5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 status7 status6 status5 status4 status3 status2 status1 status0 downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 45 maxim integrated table 42. status byte (reads from 10h)table 43. spi commands (writes to 10h) (all commands are issued by writing spi address 10h.) soft reset software reset allows the user to reset the part through writes to the serial port. a soft reset can be performed by writing the reset code 5ah to address 10h. upon initiation of soft reset, the fuse memory is read and loaded into the spi registers. see the 3-wire serial peripheral interface (spi) section for further detail. the reset is self-clearing, subsequent serial-port write(s) are not needed to clear the reset condition. afe programming and data transfer the internal analog front-end (afe) and adc are pro - grammed through a common serial-port interface. there are 48 user-programmable bits in the adc that store afe control information. these bits are written to registers 0ah to 0fh in the adc, and transferred to the afe shift registers when aeh is written to register 10h. the user must provide at least 50 clock cycles on sclk after this control word is written to complete the data transfer to the afe. to verify that the data has been transferred to the afe, poll address 10h until bit 6 is 0. as a final step, write 00h to address 10h. changes in registers 0ah to 0fh do not take effect in the afe until this transfer is complete. cwd beamformer programming and clocking programming of the cwd beamformer occurs in the following sequence: 1) during normal cwd mode, the mixer clock (lo+, lo-) is on. loon is high. 2) shut off the mixer clock (lo+, lo-) or pull loon low to start the programming sequence. 3) write the phase and channel shutdown information into the proper control registers. 4) transfer the phase information from the control reg - isters to the afe (see above) and wait for the write to complete. turn on the mixer clock and set loon to high to start beamforming (the afe shift registers can also be written with the mixer clock running and loon set low). if turning on the mixer clock source, the clock must turn on such that it starts at the begin - ning of a mixer clock cycle. a narrow glitch on the mixer clock is not acceptable and could cause meta - stability in the i/q phase dividers. if using the loon control to turn on the mixer clock, the loon signal must be synchronous to the lo clock, and it must meet the minimum setup time specification. status bit no. read value description 7 0 reserved 6 0 1 = afe load in progress; 0 = load complete 5 0 or 1 1 = rom read in progress 4 0 or 1 1 = rom read completed, and register data is valid (checksum ok) 3 0 reserved 2 1 reserved 1 0 or 1 reserved 0 0 or 1 1 = duty-cycle equalizer dll is locked command write data description soft reset 5ah initiates software reset transfer data to afe aeh initiates transfer of data in adc registers 0ah to 0fh to afe downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 46 maxim integrated 5) to program new cwd phase information, turn off the mixer clock and/or set loon low and repeat steps 1?5. 6) for switching between vga and cwd modes without reprogramming the spi registers (fast-mode switch - ing): when changing from cwd mode to vga mode, nothing needs to be done to maintain the afe pro - gramming settings. when switching from vga mode to cwd mode, the user must provide a cs pulse after the cwd pin goes high to initialize the cwd beam - former phase registers. this pulse must occur 100ns or more after the rising edge of the cwd pin, and must be at least 80ns in width. applications information ultrasound-specific imd3 specification unlike typical communications applications, the two input tones are not equal in magnitude for the ultrasound- specific imd3 two-tone specification. in this measure - ment, f 1 represents reflections from tissue and f 2 rep - resents reflections from blood. the latter reflections are typically 25db lower in magnitude. im3 performance for the device is measured with the smaller tone at -25dbc in order to more accurately resolve the small im3 products over the thermal noise floor. the imd3 product of interest (f 1 - (f 2 - f 1 )) presents itself as an undesired doppler error signal in ultrasound applications (see figure 22 ). figure 22. ultrasound-specific imd3 ultrasound imd3 -25db f 1 - (f 2 - f 1 )f 2 + (f 2 - f 1 ) f 1 f 2 downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 47 maxim integrated typical application circuit inc1 v cc3 c27100nf c15 100nf c16100nf c25 100nf r1 120 i r2 120 i r3120 i r4120 i zf1 in1v cc3 v cc5 ci+ci- cq+ cq- lo+ lo+ cwd cwd loonovdd out1- i.c. n.c.refio loon lo- lo- shdn shdn avddavdd zf8 in8 inc8 v cc5 v cc3 v cc5 v cc3 v cc5 v ref c24100nf a1 l1 b2 b12 c11 c12 d11 d12 e11 e12 f11 f12 g10 ovddovdd f10 g11 g12 h11 h12 j11 j12 k11 k12 l11 a2 a3 m1 m2 l3 m3 m6 l7 m7 m4 l4 a5 b5 a6 b6 a7 b8 b7 a8 b9 a9 a10 b10 a12 b3 a4 b4 v cc5 avdd ovdd c22100nf out1- ovdd 11v c26 100nf c23 100nf c17 100nf c19 100nf c18100nf c20100nf v cc5 v cc3 v ref gc+ m5 v g + gc- l5 v g - clkin+ clkin+ cs cs clkin- sclk l8 m8 l10 m10 m11 clkin- sclk sdio sdio l6 avddavdd avdd in2 in1 zf2 in2 inc2 b1 c2 c1 c30 2.2nf c28 2.2nf c29 4.7nf c1 4.7nf out2+ out2+ out2- out2- out3+ out3+ out3- out3- out4+ out4+ out4- out4- clkout+ clkout+ clkout- clkout- frame+ frame+ frame- frame- out5+ out5+ out5- out5- out6+ out6+ out6- out6- out7+ out7+ out7- out7- out8+ out8+ out8- out8- gnd in3 zf3 in3 inc3 d2 d1 e2 c2 2.2nf c3 4.7nf in8 in4 zf4 in4 inc4 e1 f2 f1 c4 2.2nf c5 4.7nf agag f3 g3 c6 47nf in5 zf5 in5 inc5 g2 g1 h2 c7 2.2nf c8 4.7nf in6 zf6 in6 inc6 h1 j2 j1 c9 2.2nf c10 4.7nf l12 c14 4.7nf c13 2.2nf in7 zf7 in7 inc7 k1 k2 l2 c11 2.2nf c12 4.7nf MAX2079 c3 c4 c5 c6 c7 c8 c9 c10 a11 d3 d4 d5 d6 d7 d8 d9 d10 e3 e4 e5 e6 e7 e8 e9 e10 f4 f5 f6 f7 f8 f9 g4 g5 g6 g7 g8 g9 h3 h4 h5 h6 h7 h8 h9 h10 j3 j4 j5 j6 j7 j8 j9 j10 k3 k4 k5 k6 k7 k8 k9 k10 l9 m9 gnd bumps c21100nf out1+ out1+ b11 ovdd m12 ovdd downloaded from: http:///
low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 48 maxim integrated chip information process: bicmos/cmos ordering information + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part temp range bump-package MAX2079cxe+ 0 n c to +70 n c 144 ctbga MAX2079cxe+t 0 n c to +70 n c 144 ctbga package type package code outline no. land pattern no. 144 ctbga x14400m+1 21-0492 90-0347 downloaded from: http:///
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 49 ? 2012 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. low-power, high-performance, fully integrated octal ultrasound receiver (octal lna, vga, aaf, adc, and cwd beamformer) MAX2079 revision history revision number revision date description pages changed 0 8/11 initial release ? 1 10/12 fix errors and update typical operating characteristics downloaded from: http:///

▲Up To Search▲

Price & Availability of MAX2079

	To Download MAX2079 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .